how can we calulate the time period of clock for the circult with lag skew??

sana_akhtar · Apr 21, 2012

Can anyone tell how lag clock skew lead to hold violation?? and how we will calculate the time period for the circuit if the clock to one register has lag skew by some ns???

sam536 · Apr 21, 2012

Too much Positive skew will lead to hold violations. For ex: Start point clock latency is 1ns and end point clock latency is 2ns. The combo logic between First flop and second flop is 300ps. There is hold violations of ~700ps. here the skew is 1ns (2ns -1 ns). So you need to reduce this skew to get rid of hold violations. If you need this skew requirment for other purposes, need to add hold buffers of 700ps delay to meet hold requirement.

Do you mean Clock period in second question?. Clock period doesnt depend on the skew values. Correct me if I am wrong.

Regards, Sam

sana_akhtar · Apr 22, 2012

sorry by clock period i meant then how much time it will take from one flop to other flop?

how can we calulate the time period of clock for the circult with lag skew??

sana_akhtar

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sam536

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how can we calulate the time period of clock for the circult with lag skew??

sana_akhtar

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