Too much Positive skew will lead to hold violations. For ex: Start point clock latency is 1ns and end point clock latency is 2ns. The combo logic between First flop and second flop is 300ps. There is hold violations of ~700ps. here the skew is 1ns (2ns -1 ns). So you need to reduce this skew to get rid of hold violations. If you need this skew requirment for other purposes, need to add hold buffers of 700ps delay to meet hold requirement.
Do you mean Clock period in second question?. Clock period doesnt depend on the skew values. Correct me if I am wrong.
Regards, Sam