I bet the R1 in your figure is not meant to be there or rather u were trying to model the parasitics.
The question u have to ask yourself is:
1. How slow is V2's ramp? What's the purpose of ramping this slow?
2. From diagram, your cap is charged to the supply, or is it an input voltage that
u wanted to compare with V2?
From what I can see is, if your R1 is a pure parasitic, which could probably be in the range of more than 1G, there's simply no other way where u could do better. This is because even if u r buffering it, ur cap would still be inadvertently connected to some parasitic leakage path.
Maybe you could do some periodic refresh on the cap. like in memory cell?
Perhaps, u want to tell us what is it that u r trying to do with this circuit to make us understand better.