how can i retain the charge at node v1?

[arsenal]

as shown in the attached pic,
R1 is to pull down the node of v3,
switch s1 will be on for sometime and c1 will be charged to vdd=1.5v
then s1 will be switched off, and v2 will be decreased from vdd,
when v2<v1-vtp, then v3 will turn on N1 and v4 will be pulled down,
and the problem is when v2 is going down and P1 is on, then c1 will be
discharged and v1 will decrease(s1 is off), then if v2 decrease slower than
the time constant of c1.(R1+Rp1), then v3 will never be high enough to turn
N1,(C1 is integrated, so it can not be large)
then, how can i hold the charge at v1 without using amplifiers ? thanks a lot

 

[aryajur]

Why not try increasing R1?

 

[lastdance]

I bet the R1 in your figure is not meant to be there or rather u were trying to model the parasitics.

The question u have to ask yourself is:
1. How slow is V2's ramp? What's the purpose of ramping this slow?
2. From diagram, your cap is charged to the supply, or is it an input voltage that
u wanted to compare with V2?

From what I can see is, if your R1 is a pure parasitic, which could probably be in the range of more than 1G, there's simply no other way where u could do better. This is because even if u r buffering it, ur cap would still be inadvertently connected to some parasitic leakage path.

Maybe you could do some periodic refresh on the cap. like in memory cell?

Perhaps, u want to tell us what is it that u r trying to do with this circuit to make us understand better.

 

[arsenal]

I bet the R1 in your figure is not meant to be there or rather u were trying to model the parasitics.

The question u have to ask yourself is:
1. How slow is V2's ramp? What's the purpose of ramping this slow?
2. From diagram, your cap is charged to the supply, or is it an input voltage that
u wanted to compare with V2?

From what I can see is, if your R1 is a pure parasitic, which could probably be in the range of more than 1G, there's simply no other way where u could do better. This is because even if u r buffering it, ur cap would still be inadvertently connected to some parasitic leakage path.

Maybe you could do some periodic refresh on the cap. like in memory cell?

Perhaps, u want to tell us what is it that u r trying to do with this circuit to make us understand better.

thanks a lot,
i wanna use it as a discharging path (by v4) in a power on reset and power down reset circuit while with zero power when reset is over.
and c1 will be charged to the trippoint and v2 will decrease from vdd, when vdd is going down a vtp than v1, then n1 can be turn on and pull v4 down.
r1 is not parasitics and it is used for pulling down v2 when vdd is high,i.e.,power is up, and v4 should not be pulled down.
and because of the path of r1, when v2 is decreasing, the charge will be discharged , therefore if the ramp time of v2 is very slow, the function mentioned above will never be accomplished.

then can u give me some circuit as power-on-reset and power-down-reset while consuming zero power when power is up?

thanks a lot