I'm not sure what you mean by "high level", but here's a Verilog module that uses two Xilinx DCM frequency synthesizers and a counter to divide 4 MHz down to 44.1 kHz.
#968496
An esay way is to use the Xilinx Core generator. It will guide you through the process and generate an HDL template that you can copy and past on your design.
You can also refer to your device user's guide for the clocking ressources and it will give you examples on how to instanciate a DCM.
Hope this help you.