hi all,
i m a newbie and i have the same problem (flattening my netlist).
Here's the exact problem: I synthesized my verilog design using RC and I wanna feed the synthesized netlist to Primetime. For some reason "read_verilog synthesized.v" cannot read a hierarchical netlist, since all modules become black boxes. But, if I declare as my top module a module that does not reference other modules, then primetime reads it without complaints. So I assume that the hierarchy is responsible for these black boxes. Long story short, I wanna flatten my synthesized gate-level netlist so that I only have 1 module. Is there any easy (newbie-friendly) way to do so? I dont have access to magma tools; just RC, cadence encounter, synopsys primetime.
thanks thanks
-Kostas