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Yes . You right. I want to know what am I do when I equivalance checking between rtl and netlist scan and clock inserted but the scan is not stitcing state.
If you are interested for LEC, you just have to provide the constraints.
If your device is not stitched and only scan replaced, no need to do LEC as there is not any DFT connection.
When you do synthesis using Synopsys DC Compiler, .svf file is generated for particular synthesis, we just need to provide .svf file to the Synopsys formality tool.
You can get the reference script inside the tool manual.
By doing this, you can do the LEC between RTL and Netlist.
Such type of cases, you can handle at synthesis stage.
We just have to set some variables/command, so this type of naming convention would not change. I don't remember the exact commands/variable but you can find it in the tool manual itself.
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