This is a classic problem... But first we need more info:
What kind of FF? (J-K, Toggle, D-gates)
Do they have set/reset?
One way of implementing this with half the flip-flops is to have an asynchronous reset. Is a brief glitch allowed (i.e. can you implement a glitch filter) ?
The two-bit D flip-flops Q[1:0] are counting like this way "00 01 10" repeatively.
D[1:0] are the data inputs of the flip-flops Q[1:0].
D[0]= ~Q[1] & ~Q[0];
D[1]= ~Q[1] & Q[0];
another D flop-flop HCDLY is clocked by the inverted clock to shift Q[0] for half clock cycle.
the final 50% duty cylce with no glith & minimum area = Q[0] | HCDLY