How can a differential signal be applied to the input of the ADC in pipeline design?

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in pipeline design for ex: Does 10 Ms/s means that the clock signal will be 10 MHz??
And what is differantial input? How can be applied a differantial signal to the input of the adc? For ex: a ramp function is applied to the positive input, than what will be applied to the negative input?

Thanks for your help.
 

Re: pipeline questions

Yes, with most pipeline or flash ADC, the clock is equal to sampling rate. Recommended and required input signal is documented in datasheet. Generally, true differential input signal is recommended for highest performance, but single ended drive (biasing the other input at mid voltage) is also possible with most differential input ADC. Differential input signal can be provided by a fully differential amplifier, e. g. Analog AD813x, TI THS45xx or a transformer for RF signals.
 

pipeline questions

want to design 12 bit pipeline adc
can any one help me?
thanks
 

pipeline questions

u can applied ground
and make ramp change from (+ -) range
or make acertain value for ramp(0 4)and -ve terminal be (2)
thanks
 

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