Thats a sim you show. First I would ask what timestep are you using, something on
order of 10 nSec should be used.
Two sim does not have stray L in it due to layout, PCB, possible transient even higher.
Three verify situation with PCB layout and actual probing.
Four even though "most" test programs have margin in them thats typical margin
at room test put into test program. Forum frequently gets asked by users is can they
violate datasheet specs. Sure, go ahead, that will result in early retirement for you
when management figures out you designed with no margin.
Landfills are full of margin-less designs, sad commentary on engineering.
Regards, Dana.