How are the setup and hold time values calculated for a dflipflop?

[shankar]

for a dflipflop the setup time and hold time is 1 ns can any one explain how this value is calculated

 

[karthi_mit2003]

Re: setup and holdtime

setup time and hold time are calculated based on the combinatio delays of the circuit and it follows from the formula
tcmax+tpmax<=tclk-tsu;
tck>=tpmax+tcmax+tsetup;
tcmax=maximun combinational delay
tpmax=maximun sequential delay
tsetup=set up time
tclk=clock period

and hold time is calculated based on minimum delay of the circuit.

 

[nemolee]

Re: setup and holdtime

Every cell have itself setup and hold time. Different process will have different value. So setup and hold time are based on design.

 

[shankar]

setup and holdtime

i am designing a synchronous adder .
my adder operating at 10 ns.
how can set setup time and hold time for flipflops
setuptime=?
holdtime=?
tclk=10ns.

 

[zeese]

Re: setup and holdtime

If you want to compile your design using softwares like design compiler or
something similar to it, you don't need to know or set the setup and hold time.

Setup and hold time are dependent on the technology library, or dependent
on the fab that provides the cell. Different vendors fabricate cell with different
setup & hold time.

Anyway, if you still want to approximate the value of setup & hold time,
one thing you can do is compile your design first in design compiler, and
make sure you setup the target technology library. After you compile,
you see you timing report, there, you can see the setup & hold time value.

Another way, just read the technology library files. It should mention the
all the parameters of the cell.

The one that I'm dealing in my work sometimes has setup of 0.4ns, and hold
of 0.05 ns.

Another thing I'd like to mention, setup & hold time does not affected
by the clock frequencies. Please correct me If I'm wrong. This is what I
think.

 

[power-twq]

Re: setup and holdtime

you can study a DFF's internal structure,

I think you'll get it.

best regards

for a dflipflop the setup time and hold time is 1 ns can any one explain how this value is calculated

 

[dBUGGER]

Re: setup and holdtime

for a dflipflop the setup time and hold time is 1 ns can any one explain how this value is calculated

hi,
Any FF's internal structure if you see you will find that there are two NAND or NOR gates whose output goes as input to the other. Now when the clock edge comes it comes at the same time to both the gates.
Consider the case that the signal changes just near to the clock edge so that the output due to this has not propagated to the other input. So we have two different data now, right, and then you cannot precisely say what will be the output as one may drive the reverse of what the other is driving. So the data must be given sufficient time so that it propagates through to the gate output and back at the input to the other gate. This is what i think. Please correct me if anything is wrong.
Thanks and regards,

 

[zeese]

Re: setup and holdtime

Try to take VLSI course, where you'll have to study
the internal structure of flip flop, delays, resistance,
and capacitance, and do the layout. You'll get a clear
picture. Or, just read a VLSI book.

 

[nittinsharma80]

Re: setup and holdtime

Hi
consider the flop's transistor based circuit and then read the following paper.
It describes the setup and hold requirements concept for BJT based tr..

 

[funster]

Re: setup and holdtime

The atachment is the schematic for a DFF,

from this schematic, you can see that

data input must be stable before posedege clock edge for

some time, this is called setup time,

data input must keep stable for some time after posedge clock edge,

this time is called hold time.

for detailed calculation, you can calculate them from schematic,

that's not tricky.

best regards

for a dflipflop the setup time and hold time is 1 ns can any one explain how this value is calculated