Oct 22, 2005 #1 N nani_1981 Newbie level 4 Joined Oct 20, 2005 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,325 Hi, I was asked in an interview that "Is Functions and Tasks are technology dependent and if so, How?" Can anyone help me with answer. Thank you
Hi, I was asked in an interview that "Is Functions and Tasks are technology dependent and if so, How?" Can anyone help me with answer. Thank you
Oct 24, 2005 #2 C claint Member level 5 Joined May 21, 2004 Messages 94 Helped 5 Reputation 10 Reaction score 2 Trophy points 1,288 Activity points 762 Re: Functions and Tasks No.
Oct 25, 2005 #3 E eixeix Newbie level 4 Joined Feb 4, 2005 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 54 Re: Functions and Tasks Are you talking about functions and tasks in Verilog language?
Oct 25, 2005 #4 A anjali Full Member level 3 Joined Aug 16, 2005 Messages 173 Helped 14 Reputation 28 Reaction score 6 Trophy points 1,298 Activity points 3,033 Re: Functions and Tasks the term 'technology' comes from synthesis not at simulation. functions & tasks are nonsynthesizable. they can be used at simulation level. so they are not 'technology dependent'.
Re: Functions and Tasks the term 'technology' comes from synthesis not at simulation. functions & tasks are nonsynthesizable. they can be used at simulation level. so they are not 'technology dependent'.
Oct 27, 2005 #5 E eeeraghu Full Member level 4 Joined Jun 3, 2005 Messages 221 Helped 26 Reputation 50 Reaction score 9 Trophy points 1,298 Activity points 3,384 Re: Functions and Tasks Hello Anjali, oops, i hope functions are synthesizable, regards
Oct 27, 2005 #6 N no_mad Full Member level 5 Joined Dec 10, 2004 Messages 271 Helped 30 Reputation 60 Reaction score 11 Trophy points 1,298 Location Naboo Activity points 2,489 Functions and Tasks hi, eeeraghu is right. Function is synthesizable. Usually, we use function to model combinational logic. -no_mad
Functions and Tasks hi, eeeraghu is right. Function is synthesizable. Usually, we use function to model combinational logic. -no_mad
Oct 27, 2005 #7 N naveen reddy Junior Member level 3 Joined Jun 2, 2005 Messages 28 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,525 Re: Functions and Tasks hai i think you are asking about functions and tasks in verilog functions and tasks are not synthesible in verilog in simulation level you can use them but in synthesis you cannot use tasks and functions i think this helps you bye
Re: Functions and Tasks hai i think you are asking about functions and tasks in verilog functions and tasks are not synthesible in verilog in simulation level you can use them but in synthesis you cannot use tasks and functions i think this helps you bye