hot spot in a typical processor

[mehran1367]

i want to find the hot spot of a processor. how can i do that?

plz
help

 

[jrwebsterco]

Be more specific - technically define what you mean by "hot spot" and also clarify whether you refer to e.g. a physical packaged die or an IC layout analysis.
Explaining what you are ultimately trying to achieve might also help get more useful replies.

 

[mehran1367]

well, i have a processor. i have seen the hot spot temperature map of an IBM processor in a book. it was written that the pipeline is the hot spot. i want to find myself. can i use design compiler ?

 

[jrwebsterco]

Since you mention DC, you must be referring to the std-cell implementation flow for a processor design that you are involved in.
There are EDA tools that can analyze such things, but ...
-> You need to have the P&R layout already done.
-> You need to create some kind of switching-activity file (e.g. a VCD file from a simulation run).

Synopsys' PrimeTime PX comes to mind - but there might also be tools from other EDA companies.

Regarding DC, you might be able to get useful results using Power Compiler inside of DC-Graphical, but it would be an average analysis only (not peak/dynamic), and also not sure about how useful of a layout plot it can show you.
(but you'd need the add-on DC-Topo and DC-Graphical and Power Compiler licenses)

 

[mehran1367]

I have DC-graphical and i have vcd or saif file . i do not know how to create the layout. and i donot know how to create the map. canyou help me plz.

 

[jrwebsterco]

If you are a licensed Synopsys user then you should contact your local Synopsys AE or Account Manager and they can help you get going.
You should also register at Synopsys' SolvNet support site and find all sorts of tutorials and training presentations, complete tool documentation, project setup templates and so on.
I simply do not have the time for what you ask - there is no quick & easy alternative to becoming familiar with how DC-Topo and -Graphical must be setup and run to layout/place a design during synthesis.
And to clarify, I am not personally familiar if and how Power Compiler can be used to display a power gradient (hot-spot) image inside of DC-Graphical.
If you are already familiar and comfortable with std-cell ASIC design-flow concepts and already know how to setup & run DC then you should be able to help yourself using the references I mention above.

 

[mehran1367]

ok, one more question. i can find the power of each unit and i can find the area of each unit. is it true to divide the power of each unit on area . so i have (uw/area) for each unit. so the unit with the max one is the hot spot. is it true?

 

[jrwebsterco]

If by "unit" you mean a hierarchical block of the overall processor, e.g. the pipeline block of the ALU, then this could help create a rough or relative measure of temperature.
In the end, your approach might work to find the hottest (relative) block, but might not be very good at calculating the actual (absolute) temperature.
But it is also good to at least stay aware of a few other factors.

The area that is being reported to you might only be the raw std-cell area, and is not the actual block's layout area (cells could be spaced somewhat apart from each other - not abutted up against each other, and there is also area lost to the supply-rails, and this "utilization" factor could vary for different blocks).
Blocks can also be stretched apart during P&R to deal with long routes while still meeting timing.

Clock trees and high-fanout buffers might not be in the design before P&R, and you might not be seeing the power due to buffers that are inserted near the block you are reporting.
Clock transition times likewise might be estimated before P&R, but after clock-tree insertion they might be faster and thus the flip-flop internal power could really be lower.

If you are using Power Compiler, then you are only reporting average power, which can be very dependent on the type of simulation activity that took place during the portion of time that you start and stop capturing the VCD or SAIF.
(e.g. if you captured the initial reset-release time of a simulation, you will artificially lower the average activity far below the peak activity)

Finally, if you are really wanting to estimate actual temperature, things start to get messy ...
Temperature can be tricky to calculate because you need to know what the temperature coefficient of the local area of the die is.
There is also dissipation going on at the same time - this relates to thermal relaxation constants relating to how quickly over time heat energy will get dynamically wicked away from where it is generated.
Temperature coefficients are more commonly available for the entire package/cavity design, and relate to the power/temperature ratio of the packaged die - but not to a localized hot-spot like you want.

Anyway, hopefully you are only trying to get a rough determination of the hottest block.