Hi, yes the timescale was correctly set in the environment and test bench. Before going into the debugging, I want to clarify the constraints I've set in synthesis and P&R.
1. For the synthesis, the propagated clock is used to estimate the latency in the clock network and therefore we have a realistic slack time, am I right ?
2. Can we use the same "propagated clock mode" at the beginning of P&R (as was in synthesis) and perform the optimizations ? or should the clock mode be always ideal in the constraint file at the beginning of the P&R and then after the CTS, P&R calculates the real network delay ?
3. Should the clock uncertainty defined in P&R constraints be always smaller than the uncertainty in synthesis ?
Thanks
ranaya