damn_bkb
Newbie level 3
xinlinx hold errors
Hi i have a design which has a lot of Hold errors due to a very high skew in a clk which is routed through a BUFG. The FFs has cross clock domains but this global clock skew is causing the hold errors. How can i solve this. Does a BUFR on A BUFG help.? if so will tool identify the right bufr or sdh i direct it according ?
Thanks in advance
Hi i have a design which has a lot of Hold errors due to a very high skew in a clk which is routed through a BUFG. The FFs has cross clock domains but this global clock skew is causing the hold errors. How can i solve this. Does a BUFR on A BUFG help.? if so will tool identify the right bufr or sdh i direct it according ?
Thanks in advance