hold errors with global clock bufs

[damn_bkb]

xinlinx hold errors

Hi i have a design which has a lot of Hold errors due to a very high skew in a clk which is routed through a BUFG. The FFs has cross clock domains but this global clock skew is causing the hold errors. How can i solve this. Does a BUFR on A BUFG help.? if so will tool identify the right bufr or sdh i direct it according ?

Thanks in advance

 

[yx.yang]

hold errors

In my opinion, the tool can't calculate the setup/hold timing right for FFs that cross clock domain. It's the design architecture that make the circuit work(special signal synchronization circuit).

 

[pev]

xilinx ise tnm tnm_net

BUFR is a regional clock buffer. Use on clock capabile inputs not global clock inputs.

The tool cannot calcluate timing for FFs that cross clock domains unless you specify that the clock are dependent.(if your using Xilinx ISE look into using TNM_NET / TNM).
Note: if the clocks where define from the same original clock (ie using DCM) then the tool should have already work this out for you.

If the clocks are not depenet you can still specify the minimum delay between clock domains using:
TIMESPEC <name> = FROM <> TO <> <Delay> ns
(I haven't had this one yet)

Or else you can just tell timing analysis to ingnore the FF using TIG.

The Xilinx Timing constraints guide is your friend (if your using Xilinx).
**broken link removed**

I'm sure there is Altrea equivanet constraints to these.

 

[damn_bkb]

cross clock domains:

thanks guys..
The problem is the clocks are both independent. i have a sort of asynchronous RAM. I read by a slow clock. I get a lot of hold errors. dueto too high a clock skew. Is it okay to jusst give a tmg group , or is ter a way to reduce timing skew on that clk.
The skew is on a 66mhz clk, its as high as 15ns.

 

[pev]

xilinx tig constraint clock errors

I agree with with yx.yang the design need to handel the asyncronise signals. But you at least still should tell the Map/ Place and rount tool not to worry about them using (TIG) If they are flaging a timing error.

Is the skew come from outside or inside the FPGA or inside?

If inside somthing sounds wrong try using a DCM (with feedback from BUFG).

 

[damn_bkb]

cross clock tig

hi guys,
The issue has got a much better timing if i use a DCM and a bufg combo, instead of a simple bufg. Is it always true that it can happen or is it due to a specific case as mine in which the placement just got better with a DCM?