hold checks on half cycle paths

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asicganesh

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How PT does hold check for half cycle paths?
 

Lets say clk edges are 1 2 3 4

For HOLD capture clock edge 1
For HOLD source clock edge 2
 

Hi friend,
Half cycle path scenario like data Launch through +ve edge and Capture through _ve edge fp.
L-clk period 2: +ve edge is occurred 0 2 4 6 8 10
C-clk period 2: -Ve edge is occurred 1 3 5 7 9 11

Setup check: at edge 2 at L-clk : C-clk setup check edge 3
Hold check : at edge 2 at L-clk :C-clk hold check edge 1 ...it means in half cycle path hold check we will get half cycle more hold margin.So will get large +ve slack

Correct me if it is wrong
Thanks
 

You are right. Hold is relaxed and Setup is more strict when you have half cycle paths
 

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