[SOLVED] histogram computation?

[yupina-chan]

hi. i am trying to make a module which computes for histogram. i have 8 bins and below is my code. also, i included a testbench. i can't seem to make it run. i am a beginner in verilog. pls, i need help in making this work. hints will be of big help. thanks in advance.

module histogram(data_in, out1, out2, out3, out4, out5,out6,out7,out8, clk);
output reg [7:0] out1;
output reg [7:0] out2;
output reg [7:0] out3;
output reg [7:0] out4;
output reg [7:0] out5;
output reg [7:0] out6;
output reg [7:0] out7;
output reg [7:0] out8;
input [7:0] data_in;
input clk;
 
always @ (posedge clk)
	begin
			if (data_in >= 8'b11100000)
			begin
				out8 = out8 + 1;
			end
			else if (data_in >= 8'b11000000)
			begin
				out7 = out7 + 1;
			end
			else if (data_in >= 8'b10100000)
			begin
				out6 = out6 + 1;
			end
			else if (data_in >= 8'b10000000)
			begin
				out5 = out5 + 1;
			end
			else if (data_in >= 8'b01100000)
			begin
				out4 = out4 + 1;
			end
			else if (data_in >= 8'b01000000)
			begin
				out3 = out3 + 1;
			end
			else if (data_in >= 8'b00100000)
			begin
				out2 = out2 + 1;
			end
			else if (data_in >= 8'b00000000)
			begin
				out1 = out1 + 1;
			end
end

endmodule

`timescale 1ns/1ps
module histogram_tb;
reg [7:0] data_in;
reg clk;
wire [7:0] out1;
wire [7:0] out2;
wire [7:0] out3;
wire [7:0] out4;
wire [7:0] out5;
wire [7:0] out6;
wire [7:0] out7;
wire [7:0] out8;

histogram uut(.data_in(data_in),
				.clk(clk),
				.out1(out1),
				.out2(out2),
				.out3(out3),
				.out4(out4),
				.out5(out5),
				.out6(out6),
				.out7(out7),
				.out8(out8)		
				);
initial begin 
clk=0;
#10
data_in=13;
#10
data_in=23;
#50
data_in=70;
#10
data_in=190;
#20
data_in=23;
#30
data_in=23;
#30
data_in=230;
#30
data_in=230;
#400;
$finish;
end
always begin
#10
clk=!clk;
end
endmodule

 

[std_match]

What result do you get?

You need a way to set an initial value for your out1 - out8 outputs.
This is normally done with a reset signal.

 

[yupina-chan]

the output is 'xxxxxxxx' for outputs from out1 to out8

i will try doing what you said by initializing the outputs. thanks

 

[yupina-chan]

thanks it worked :-D