Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
About four years ago I implemented a Hilber transform in a spartan 3 FPGA.
From memory the Hilbert transform was structurally the same as an FIR filter where the filter coefficients corresponded to that required to implement a Hilbert Transform.
Basically I believe each of the Hilbert transform coefficients were stored at an address in RAM. This was a long time ago but I beleive I took the input passed it into a first in first out array. At each clock I simply multipled each address in Ram by the corresponding delayed input in the FIFO array and added the result, then shifted the FIFO array.
Hope this helps
Added after 3 minutes:
Actually its funny, I remember going to an interview for a job with an example of this Hilbert Transform I had written in VHDL.
I left the interview without a job and without the code. I believe the interviewer had actually stollen my work.