hi rfmw, it's a system level design, not chip level.
your advice are appreciated.
I am studying a design where the design uses PLL chips to synthesize the clock in PECL.
Distribute all the clock in PECL.
and ultimately change it to ttl level.
Since it is ultimately changed into TTL level for the electronics system, is there any specific reason why I need to distribute it in PECL's form ?
Also, I have an idea to replace all the micrel-synergy chipset using FPGA. e.g Altera's PLL or Xilinx DCM. is that a good idea? or a separate chipset is better ?
Added after 1 minutes:
hi rfmw, it's a system level design, not chip level.
your advice are appreciated.
I am studying a design where the design uses PLL chips to synthesize the clock in PECL.
Distribute all the clock in PECL.
and ultimately change it to ttl level.
Since it is ultimately changed into TTL level for the electronics system, is there any specific reason why I need to distribute it in PECL's form ?
Also, I have an idea to replace all the micrel-synergy chipset using FPGA. e.g Altera's PLL or Xilinx DCM. is that a good idea? or a separate chipset is better ?