Hi,
That's 2.5us/period, 2,500 nanoseconds. With a 50/50 duty cycle like a square wave that gives 1.25us, 1250ns for (using BJT language) delay, rise, storage and fall times. No delay is physically impossible, much to our chagrin... You need to look for devices that meet a realistic calculation of what amount of delay the application can tolerate. All I can generically think of are buffer gates suitable for > 8 fanout fed from avoltage divider and feeding back into level shifter stage such as MOSFETs.