As you cannot change the ASIC code, you cannot change what is probably the root of the behavior you complain.
But you can try to act not on cause, but on symptoms. One idea: you can try to find not-used paths and relax or even completely ignore the timing requirement.
For example, external reset timings usually can be completely ignored. As you seems to use a huge combinational logic, maybe there are some critical paths that do not need a timing constraint.
Other try would be to manually fix some main blocks inside the FPGA (DSP, block rams) in a position that have good routing results. Unfortunately, this is quite empirical and may take a lot of time as well.