High speed serial data process method require

[shahrol_hisham]

Hi,

I would like to develop the high speed serial data system. The speed suggest is 1Gbps. It is possible to used the controller 16 bit PIC24Fxxxx the max clock is 2MHz?. Or need to used other controller.... for information the data physical medium is fiber optic. I used module for the optical side the input for module is differential input/output tx+ tx- rx+ and rx-.

Can anyone give me an idea in what the best controller to used and how to sample the high speed serial data and how to develop this system .

thank in advance.

 

[karesz]

Hali,
If you have a datalinc with 1 Gbps >> you must know, that it exists a lot of serialyzer/deserialyzers on the market for 8/16/24/32 bit with systems...
Has your PIC enough performance to handle so adata volumen, what is your goal at all pls?
K.

 

[shahrol_hisham]

Hi karesz,

Thank for reply....

Actually I try to sending and receiving data using the fiber optic like the FTTH system. I found the TI product for serialyzer/deserialyzers TLK1211. But I not sure that the controller can handle the data at the speed.
What the requirement need for process the data at the speed?

 

[FvM]

Neither a PIC24 nor most usual microcontrollers can handle data at that speed. Furthermore the term "process the data" is
very unclear. You may want to mention which operations you intend to perform with the data to allow suggestions for a
suitable hardware platform.

 

[shahrol_hisham]

The term process more refer to decode the data and do some assignment to the system. My concern is:
I not sure about the controller requirement, the PIC24 is only work for 32MHz. The reading/process power if using this controller is 32Mhz/4 =8MHz. If change to time is 0.125us. This is max time the controller can read the data. If the serial data is 1Gbps so for 1 bit it will require 1e-12sec, it is to fast for the controller like pic24F to read the data. So may be the is the method used for handle this high speed data.

Any advice.

 

[FvM]

You didn't manage to actually clarify your requirements in my opinion, but for the time being, you may want to consider
programmable logic (CPLD/FPGA) to process the data.

 

[karesz]

Hi shahrol_hisham,
Sorry, but your aspet is unclear for me; if you have (of course) such ser/deser solution in your sytem, you has the data as a parallel volumen of i.e. 16/32...Bits.
You has it to feeed to a micro/FPGA, but the encoding is maked trough your deser IC.
In all case I hade similar project so 10 years ago with such HP ICs for ~1.5Gbps/opto-line, but their are no more on the maket:-(_their does needed no more decoding_only normal datahandlings...
K.

 

[shahrol_hisham]

Are you used the microcontroller or fpga for 1.5Gbps project. If microcontroller what the microcontroller speed require to handle the data from ser/deser ic?

If I would like to develop the system using FPGA it is possible to put the MCU in the FPGA? and what the running speed?

TQ

 

[karesz]

Hi,
sorry for long wait...
In my project are used the 1.5Gbps G-Link components: HDMP 1022 & 1024.
Moderner are: 1.4Gbps HDMP1032/1034, but I didnt check_if their are on the market too?
Maybe you can apply these chip-familie too?
K.

 

[shahrol_hisham]

Hi karesz

Can you share the design with me...

the main item is what the controller that you used to integrate with ser/dser ic.

TQ

 

[karesz]

Hi Shahrol,
Sorry, but family 1022 isnt more in production_as I know, thes was the reason that I gave the more newer typ Nrs for you too...
w*w.alldatasheet.com/datasheet-pdf/pdf/113223/HP/HDMP-1032.html
In thes project we have had FPGAs (actual types from 2001...), but _sorry_ I can not share some code form it, than it was made for some firm.
K.

 

[shahrol_hisham]

Hi karesz

for your FPGA what the operational clock speed?

TQ

 

[karesz]

Hi,
Sorry, it was not my part, but I think 80 or only 40MHz(external)?
Im no more sure over their_it is 8-9 years behind us....
I remember for data output at 820MHz, some atypical value becous our Fref. (a sub clock) was at 10.4xxMHz
K.

 

[shahrol_hisham]

Hi karesz

How your fpga can read output data at high data rate from ser/dser ic.
The throughput from ser/dser ic is 1.5GHz, but your FPGA running on 40Mhz.

It is because the ser/dser have a delay circuit? if yes, so what I need is add the delay IC to my current system.....

pls advice.

 

[FvM]

The discussion apparently didn't progress much since one month...

As a first comment, it's advisable to plan the project design based on present available chips. There are huge differences in available data throughput with affordable programmable logic to state of the art 8 or 10 years back.

As a second comment, I still didn't hear a serious specification of intended data processing. It's more or less meaningless to discuss about suitable hardware without understanding the amount of data processing and all interfaces involved in it.

A 1 GBit serial data stream results e.g. in a 100 MByte/s data rate, if it's 8b/10b coded. In so far it's reasonable to plan a higher (internal) system clock than 40 or 80 MHz for the data processing design part. But the data can be deserialized also to 16 or 32 parallel bits...

Generally, you can assume, that a software processor implemented in a FPGA is not fast enough to process the data in real time (A PIC24 isn't as well). You have to consider generic parallel FPGA logic for the data processing core. Even a fast PC processor could only perform low complexity operations on the data.

 

[karesz]

Hi FvM,
If you check the HDMPs datasheet; your data is deserialaized to 16 bit words, system has mux/demux of 16, & with an + 4bit header has the 20 bit words...
Exactly thes muxing was the reason for my proposal of ca. a month ago. we applyed a extra 4x mux/demux too, I remember yet & 40 MHz for the 16 bit datawords...
At this time I can not tell more over their_sorry, than I think too, naowadays are (hopfely) more similar or better components to find or realized.
Regards!
k.

 

[FvM]

Yes, the HDMP transceiver suggestion isn't bad. My comment about considering recent chips was mainly addressing logic chips. Today you get a lot, that include Gigabit transceivers with CDR operation.

But the question was mainly about data processing system design. Clock rates and word widths must be decided from the data processing requirements, I think.

 

[shahrol_hisham]

Hi FvM and karesz,

I believe both of you are right,
Actually I would like to develop the ONU and the OLT for FTTH system, with the link speed is 1.2Gbit/s. I don't have a good knowledge on FPGA but for micro-controller yes (PIC). I believe when the data rate is to high >1Gbit/s the controller speed also need 5x greater then the data rate so the controller have enough time to process and manipulate the data. But my current controller is only capable to work up to 40MHz clock. So I wonder if there is a special technique to overcome the problem. So I can process and manipulate the data without change the hardware(controller).

TQ