high gain amplifier design (2000 V/v gain)

[pinoismo]

I want to design an op amp with the following specifications:

* Allowed transistors are the 3904 (npn BJT), 3906 (pnp BJT), 2N3819 (n-channel JFET).
* The input is a 1 mV amplitude source at 1.0 kHz riding on a DC value between -1.0V and +1.0V. The source has a 4 kΩ source resistance.
* The primary goal is to provide a 2 V amplitude sinusoidal output across a 100 Ω load with an average value as close to 0.0V as possible.
* No capacitors are allowed.
* Standard resistor values must be used.
* Supply voltage is to be provided by no more than 2(two) 9V batteries.

 

[BradtheRad]

Sounds like the assignment is to make a class AB audio amplifier. Have you a drawn up a tentative schematic?

 

[pinoismo]

Sounds like the assignment is to make a class AB audio amplifier. Have you a drawn up a tentative schematic?

I tried a differential amp cascaded with a darlington pair but nowhere close to the desired results. I also tried the class AB and still no luck

 

[BradtheRad]

Eliminating DC component on the input will be tricky since the specs say you can't use capacitors.

A JFET is mentioned among the components. This suggests a way to eliminate DC component at the input. A JFET doesn't need any specific bias. You just apply the signal... although you must arrange resistor values to set the drain and source at proper voltages, because a JFET gate should not be biased so that current goes through it. It is damaged by slight current.

The JFET will give you some gain.

A darlington pair can be 2 NPN, 2 PNP, or it can be a Sziklai pair (NPN & PNP). One configuration needs twice as high bias voltage. The other does not, which could be an advantage.

Now I see your initial post says 'op amp'. This is a differential amp rather than AB amp. You say you tried a differential amp. Does this mean you started from a long-tailed pair? Current mirror? Etc.?

Two 9 V batteries suggests a dual supply. This is what op amps typically require for easiest operation.

 

[FvM]

In a short, it's effectively impossible in a discrete transistor design without capacitors, because amplifier offsets and offset drifts are too large. An monolithic op would achieve input offset drifts, that allow to substract a fixed DC component. If the DC part is changing however, AC coupling using capacitors would be necessary as well.

 

[pinoismo]

This is what I came up with so far, a gain of about 28. In class, the only purpose of using the darlington pair was to give a high gain. and the hand calculations showed that there was a differential gain of around 5000 V/V for a problem that has the same setup as the attached circuit. can you explain why I get such a fair gain in here, and how to make it better?
**broken link removed**
**broken link removed**

 

[FvM]

In your circuit, only the differential JFET pair is providing voltage gain. A number of 28 isn't bad, I calculated an even lower value from typical 2N3819 parameters, but the part has a rather large exemplar variation of Idss and Vgsoff and no typical values specified, at least in the Fairchild datasheet.

If you replace the JFET pair by a bipolar transistor pair, you get an already higher gain, an lower input offset with real transistors. You'll need multiple gain stages to achieve the intended gain. The problem of superimposed DC voltage, as addressed in your initial post, can't be solved by a circuit like this.

 

[BradtheRad]

The 100k value in the emitter leg (R5) reduces sensitivity and reduces gain.

It also sets a high output impedance. You need a low output impedance.

Whatever value R5 is, the output transistor needs to operate at the same average resistance, in order for average output to be 0 V avg.

You need output resistances closer to the 300-600 ohm region. By reducing R5 you may get this automatically.

Not sure whether you'll need to change anything else. It depends on the degree to which bias is changed through the darlington pair.

 

[FvM]

I agree that R5 should be reduced to a reasonable level of e.g. 0.5 to 1k. I ignored the point so far. But it doesn't bring you much nearer to intended gain of 2000 or even 5000. You preferably need three stages with voltage gain to achieve it.

 

[pinoismo]

I changed the FET's with BJT's, and after checking the the voltage V(BE) of the first transistor from the left, I found that it is way less than 700 mV (around10 mV) which means that the bjt is not even in forward avtive mode. I tried to fix that but I couldn't since I have an ac current source commming dierectly to the base. any comments on that?

 

[FvM]

May be the case, if the voltage source is AC coupled, which can't be seen from your schematic, where you have a (DC coupled) voltage source with moderate source impedance.