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High Frequency PSRR in BandGap

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Megh

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banba bandgap

Hello,
Designing a sub volt (Banba Type) bandgap.
I am having problem that my low frequency PSRR is say -40dB and then the PSRR rises to -29dB at say 10MHz and then again starts reducing.
Need to improve this peaking in PSRR curve.
Please help on this.
My understanding is:
1) DC PSRR is governed by the loop gain and the Resistor devider ratios.
2) High frequency PSRR basically behaves the way (inverted image) of the gain of your loop.
If this understanding is correct then I don't see a zero (on the gain curve) near the frequency where my PSRR starts going uphill.
Please help on this
Thanks
 

dick_freebird

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dc psrr

Your forward gain in the amplifier, is only one part of
the story (and perhaps not the significant part). Look
at your bias racks and other supply-to-output paths
which "should" be supply voltage independent, but can
never -entirely- be.

Preregulating with a crude LDO is one way to bump up
PSRR, if you have the headroom. This regulator need
not be DC-fabulous, just well AC-decoupled.

You can also post-filter the bandgap with an RC if
you can tolerate a weakening of the drive (load reg
degrades, but something that only has to drive a
capacitive load might not care).
 

    Megh

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PaloAlto

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high psrr bandgap

You can move upwards in frequency the starting point of the rising slope by improving the bandwidth of the bandgap amplifier (assuming we are talking pnp-type bg)

You can move downwards in frequency the peak of the psrr response by adding more capacitance to the output node

Good luck
 

    Megh

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saro_k_82

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bandgap psrr

As dick_freebird has already said, it is the TF from the supply to the output matters for the PSRR and not the loop TF. There can be many parallel paths to the output from the supply and a presence of zero should not be a surprise.
May be the zero is prominent due to the way you have added the cap for stability. It would be hard to tell without looking at the circuit.
 

Megh

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Thanks Dick and PaloAlto,
I am going to try putting RC at the output as the bg is going to drive LDO's input cap. This seems like a brute force method (basically killing the BW) though.
BTW @PaloAlto :- Improving BW of the amplifier will shift the peaking frequency but it wont reduce the peak. So the noise @ the new frequency will still create a problem right?
I think only way to kill the psrr is to put cap at VBG output.
Please comment.
Thanks for your time

Added after 2 minutes:

sorry I meant Thanks dick_freebird...It printed ***** sorry for that one.
@saro :- I added the compensation cap between gate of the PMOSs(Whose gate is controlled by amplifier) and VDD.
 

PaloAlto

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Megh said:
Improving BW of the amplifier will shift the peaking frequency but it wont reduce the peak. So the noise @ the new frequency will still create a problem right?

Improving the BW will shift the peaking frequency, so if the falling slope created by decoupling at the output voltage is maintained, the peak rising slope is cut at a lower value, so, the peak is lower
 

toctory

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In your LDO, the reference voltage could also took from the BG output to further improve the PSRR. But some effort must be made to avoid startup problem in this configuration.
 

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