Thanks for the info buddy but I still have the doubt about the same.
While you can look up the C in your triac, it may be difficult to predict ahead of time the parsitics of the rest of the circuit or the load.
In practice you can add those components to your layout and fine tune them later based on real world testing.
Also in practice I'd turn to the simulator to experiment with values for load L (based on whatever guesses you can make about your system) and RC values.
If I increase the snubber capacitance then it will reduce the voltage overshoot at triac or optocoupler(separate circuits).
but If I increase the Resistance then the dI/dt will be reduced but increasing the voltage overshoot. Since both are vice versa...I wanted to find an optimum solution to my board since it has to be so space confined as per design requirements.
#I do not have the maths to validate the above info from any of the datasheets or application note.
So as you told if I choose a capacitor value would not that affect my dI/dt performance...How can I make a calculated
trade off between the same.
Following is what the Vishay told me about it...
There are two options to deal with this problem. The first is to use Vishay’s high dV/dt (10000 V/μs) phototriacs, because the high dV/dt will solve the problem.The second is to add a snubber similar to the one included in the circuit shown above.
The basic design process for arriving at the most advantageous snubber possible is as follows:
1. What is the highest tolerable dV/dt that a particular phototriac can withstand?(How to find this because in datasheet all values are at 25 degree celsius)
2. Use dV/dt = V/(Rs x Cs) to come up with an appropriate RC combination
But I did not understand how to find the worse case dv/dt of the Triac or Optocoupler
In the image is a method to find the dv/dt but I did not understand how...Does someone understand how to calculate it from the graph ?