Hierarchical design with SOCE

[mcdjnaja]

Hello everyone !
I am new on this forum.
I am working on the design of a MPSoC including 30 cores of microprocessor. So, this design is hierarchical and i do a bottom-up place and route. First, I place and route the RAM and the cores of processor. With SOCE, the output of this place and route is a LEF file (lefout command) that i can use for the upper level.
My problem is with the LEF file itself. For example, in the core of microprocessor, i use only M1, M2 and M3, not of all M4, M5, M6. But, the LEF file contains obstructs of the design size for M4, M5 and M6. In fact, i want to have the exact coordonates to know the transparency for each level of metal.

Thanks in advance.

 

[mcdjnaja]

nobody answered ?

 

[mcdjnaja]

Hi, my explanation is not understandable or nobody has an answer ?

 

[sakivg]

dude, can u be more clear?
let me explain what i know:
Creating partitions and bottom up : correct.
LEF out: This .lef file is used as input when working higher up the hierarchy.

i use only M1, M2 and M3, not of all M4, M5, M6. But, the LEF file contains obstructs of the design size for M4, M5 and M6. In fact, i want to have the exact coordonates to know the transparency for each level of metal.

This part of your post is unclear. If u want to use only M1,M2,M3 at core level; this restriction can be imposed during the routing phase in SOC encounter.

 

[mcdjnaja]

Hi, thanks for your response.

For the unclear part,I impose during the routing phase no level 4, 5, 6 (with createRouteBlk). But, after, when i generate the LEF corresponding to this block, I have an obstruct for the level 4, 5, 6 for the entire area of my block in spite of this level are not used of all.

 

[iwpia50s]

When you specify to use M1, M2, M3 for partitions, that's what SoCE does for the partition...it blocks all levels above what you specified...entirely.