In verilog, I need a variable to be assigned some value at beginning and another value after some time during simulation. Then how could I define this variable and how to re-assign the value?
module top;
reg a_variable; // define a variable
initial begin
a_variable = 0; // assign it some value at the beginning
#1234; // after some time
a_variable = 1; // re-assign the variable
end
endmodule
I believe this answers your question perfectly, but I doubt it helps you.
That sounds like a bad solution for the posed problem. Why? Because.
Why because? Because willy nilly usage of globals is a bad idea. And it's only non-willynilly if there is a specific reason. This is not a specific reason, this is a random idea. And as such because.
Other than that, your question is a bit vague.... care to be more specific about the scenario?