I am curious about your question, so please enlighten me on the following.
1> What is a System Verilog net-list?
As I know, netlists usually convey connectivity information and provide nothing more than instances, nets, and perhaps some attributes. Netlists are obtained from a hardware description language such as Verilog, SVerilog, VHDL, or any one of several specific languages designed for input to simulators.
2> If you have one type of netlist (assuming that you had modeled a digital circuit using SystemVerilog) why would you want to convert it to spice netlist. I don't see the relation/significance!