Help with Xilinx ISE Schematic Floorplan

[r.youden]

Hi, I have been doing a small home project with the Xilinx ISE software and a small FPGA. I am having trouble with Implementing the design, I have even taken it back to first principles and i still can't get it to work.

What I have is a series of 4 flip flops seen in the first screen shot, nothing complex there.



Now when I try and implement this and go into the Floorplan IO I don't get the options for Clock and Q0...Q3, all I get is D, C and Q, the in/out from one of the flip-flops.



It must be something very simple that I'm doing wrong, if someone could point me in the writ direction that's be great.

Many thanks in advance.

Richard

 

[r.youden]

Anybody able to help at all? I have spent the last two days going round and round in circles with this and it is so frustrating, surely this is the most straight forward aspect of the whole thing!

 

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check the map report.

I think this is getting reduced to 1 flop as you have a feedback path from the last flop to the first flop. Since all the flops will have the same init value (0) there is no need for 4 flops as they are all identical.

If you add an inverter as the input to the first flop you'll probably see all four flops.