library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab5 is
port(
RST, CLK, GO : IN std_logic;
HC : IN std_logic_vector(1 downto 0);
ABIJ : OUT std_logic_vector(3 downto 0);
SEG7 : OUT std_logic_vector(13 downto 0)
);
end entity lab5;
architecture behavioral of lab5 is
type states is (S0, S1, S2, S3, S4, S5, S6, S7);
signal D, Q : states;
signal ABUS : std_logic_vector(3 downto 0);
signal can_increment : std_logic;
begin
DFF: process(RST, CLK)
begin
if RST = '0' then Q <= S0;
elsif rising_edge(CLK) then Q <= D;
end if;
end process;
process(clk,rst)
variable cnt: std_logic_vector(3 downto 0):="0000";
begin
if (clk'event and clk = '1') then
if (HC = "00") then
can_increment <= '0';
else
can_increment <= '1';
end if;
if can_increment = '1' and HC = "00" then
cnt := cnt + 1;
end if;
end if;
end process;
D <= S0 when Q = S0 and GO = '1' else
S1 when Q = S0 and GO = '0' else
S1 when Q = S1 and HC = "11" else
S5 when Q = S1 and HC = "10" else
S4 when Q = S1 and HC = "01" else
S2 when Q = S1 and HC = "00" else
S7 when Q = S2 else
S7 when Q = S3 else
S4 when Q = S4 and HC = "01" else
S1 when Q = S4 and HC = "11" else
S5 when Q = S4 and HC = "10" else
S5 when Q = S5 and HC = "10" else
S1 when Q = S5 and HC = "11" else
S4 when Q = S5 and HC = "01" else
S7 when Q = S6 else
S2 when Q = S7 and HC = "11" else
S3 when Q = S7 and HC = "01" else
S6 when Q = S7 and HC = "10" else
S2 when Q = S7 and HC = "11" else
S5 when Q = S7 and HC = "10" else
S4 when Q = S7 and HC = "01" else
S0;
with Q select
ABIJ <= B"1111" when S1 | S2,
B"0011" when S5 | S6,
B"1100" when S3 | S4,
B"0000" when others;
WITH ABUS SELECT
SEG7 <= "11111110000001" WHEN B"0000",
"11111111001111" WHEN B"0001",
"11111110010010" WHEN B"0010",
"11111110000110" WHEN B"0011",
"11111111001100" WHEN B"0100",
"11111110100100" WHEN B"0101",
"11111110100000" WHEN B"0110",
"11111110001111" WHEN B"1110",
"11111110000000" WHEN B"1000",
"11111110001100" WHEN B"1001";
"11111111111111" WHEN others;
end architecture behavioral;