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[SOLVED] Help with VHDL UP Counter

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lamorak

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Hello,

I am working on a project for class where our robot follows a line on the ground. when the inputs H&C = "00" the robot is supposed to increment its counter by 1 and display the number on the seven segment display. However my counter is not working and i dont have a clue how to make it work.
Code:
      process
        begin 
          if (RST='0') then 
            ABUS <= "0000"; 
          elsif (HC="00" and CLK='1') then 
            ABUS <= ABUS + 1;
          end if; 
      end process;

with ABUS select
SEG7   <= "11111110000001" WHEN B"0000",
              "11111111001111" WHEN B"0001",
              "11111110010010" WHEN B"0010",

This is the counter code i am using.

Any help would be greatly appreciated!
 

amitjagtap

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you can try this process
process(clk,rst)
variable cnt: std_logic_vector(3 down to 0):="0000";
begin
if (rst='0') then
cnt <= "0000";
elsif (clk'event and clk='1') and (HC="00") then
cnt <= cnt + 1;
end if;
ABUS<=cnt;
end process;
& so on.....
Well ABUS assignment to 7seg was not clear how you are doing....
 

lamorak

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amitjagtap,
thank you for your quick reply!
Good news and bad news,

Good news is it increments when HC = 00, however, it keeps implementing every CLK rising edge while HC = 00. I only want it to implement once per HC = 00.
Any way to make that work?

the abus to 7seg works, im just using a with select statement to get the proper number to display.
 

permute

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you need some state information. eg:
Code:
if (clk'event and clk = '1') then
  if (HC = "00") then
    can_increment <= '0';
  else 
    can_increment <= '1';
  end if;
  if can_increment = '1' and HC = "00" then
    cnt <= cnt + 1;
  end if;
end if;

the can_increment register will transition from 1 to 0 after HC=00. if HC becomes a different value, then can_increment will be 1 on the next cycle, which is the earliest the HC=00 condition could come along.
 

lamorak

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thanks for the reply. I tried that, but now my counter does not increment at all. it just stays the same

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lab5 is
port(
	RST, CLK, GO : IN std_logic;
	HC   : IN std_logic_vector(1 downto 0);
	ABIJ : OUT std_logic_vector(3 downto 0);
	SEG7 : OUT std_logic_vector(13 downto 0)
	);
end entity lab5;

architecture behavioral of lab5 is

	type states is (S0, S1, S2, S3, S4, S5, S6, S7);
					
	signal D, Q : states;

signal ABUS : std_logic_vector(3 downto 0);	
signal can_increment : std_logic;
	
begin
	
	DFF: process(RST, CLK)
	begin
		if RST = '0' then Q <= S0;
		elsif rising_edge(CLK) then	Q <= D;
		end if;
	end process;

process(clk,rst)
	variable cnt: std_logic_vector(3 downto 0):="0000";
	begin
		if (clk'event and clk = '1') then
			if (HC = "00") then
				can_increment <= '0';
			else 
				can_increment <= '1';
			end if;
			if can_increment = '1' and HC = "00" then
				cnt := cnt + 1;
			end if;
		end if;
	end process;

	D <= S0 when Q = S0 and GO = '1' else
		 S1 when Q = S0 and GO = '0' else
		 S1 when Q = S1 and HC = "11" else
		 S5 when Q = S1 and HC = "10" else
		 S4 when Q = S1 and HC = "01" else
		 S2 when Q = S1 and HC = "00" else
		 S7 when Q = S2 else
		 S7 when Q = S3 else
		 S4 when Q = S4 and HC = "01" else
		 S1 when Q = S4 and HC = "11" else
		 S5 when Q = S4 and HC = "10" else
		 S5 when Q = S5 and HC = "10" else
		 S1 when Q = S5 and HC = "11" else
		 S4 when Q = S5 and HC = "01" else
		 S7 when Q = S6 else
		 S2 when Q = S7 and HC = "11" else
		 S3 when Q = S7 and HC = "01" else
		 S6 when Q = S7 and HC = "10" else
		 S2 when Q = S7 and HC = "11" else
		 S5 when Q = S7 and HC = "10" else
		 S4 when Q = S7 and HC = "01" else
		 S0;

	with Q select
	ABIJ <= B"1111" when S1 | S2,	
			B"0011" when S5 | S6,
			B"1100" when S3 | S4,
			B"0000" when others;

	WITH ABUS SELECT
		SEG7   <= "11111110000001" WHEN B"0000",
		          "11111111001111" WHEN B"0001",
		          "11111110010010" WHEN B"0010",
		          "11111110000110" WHEN B"0011",
		          "11111111001100" WHEN B"0100",
		          "11111110100100" WHEN B"0101",
		          "11111110100000" WHEN B"0110",
		          "11111110001111" WHEN B"1110",
		          "11111110000000" WHEN B"1000",
		          "11111110001100" WHEN B"1001";
		          "11111111111111" WHEN others;			       

 end architecture behavioral;

here is my code
 

TrickyDicky

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your cnt variable doesnt connect to anything, and so is removed when the design is synthesised. I think you meant to replace cnt with ABUS.
 

capitan

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you need an fsm to keep track of when you have encountered hc="00".

Code:
when state=not_encountered
       if(HC="00") then
            increment<='1';
            next_state<=encountered;
       else
            increment<='0';
            next_state<=not_encountered;
       end if;
when state=encountered       
        if(HC="00") then
            increment<='0';
            next_state<=encountered;
       else
            increment<='0';
            next_state<=not_encountered;
       end if;

or something like that.

Also note that the 7segment displays are usually time multiplexed so you need some kind of controller to drive it properly. Otherwise it will just show a faded 0000.
 

lamorak

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your cnt variable doesnt connect to anything, and so is removed when the design is synthesised. I think you meant to replace cnt with ABUS.

That did it! got it to work, fixed that and added process and end process that chunk of code and it works now!

thanks for the help everyone!
 

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