Help with verilog - Better way of implementing this?

[vakilp]

Hello,

I am new to verilog and would like your help on this. I am looking at the code below:

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Code Verilog - [expand]
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module beh_fifo (rdata, wfull, rempty, wdata, winc, wclk, wrst_n, rinc, rclk, rrst_n);
 parameter DSIZE = 8;
 parameter ASIZE = 4;
 output [DSIZE-1:0] rdata;
 output wfull;
 output rempty;
 input [DSIZE-1:0] wdata;
 input winc, wclk, wrst_n;
 input rinc, rclk, rrst_n;
 reg [ASIZE:0] wptr, wrptr1, wrptr2, wrptr3;
 reg [ASIZE:0] rptr, rwptr1, rwptr2, rwptr3;
 parameter MEMDEPTH = 1<<ASIZE;
 reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1];
 
 always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) wptr <= 0;
    else if (winc && !wfull) begin
        ex_mem[wptr[ASIZE-1:0]] <= wdata;
        wptr <= wptr+1;
    end
    
 always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) {wrptr3,wrptr2,wrptr1} <= 0;
    else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr};
    
 always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) rptr <= 0;
    else if (rinc && !rempty) rptr <= rptr+1;
 
 always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) {rwptr3,rwptr2,rwptr1} <= 0;
    else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr};
 
 assign rdata = ex_mem[rptr[ASIZE-1:0]];
 assign rempty = (rptr == rwptr3);
 assign wfull = ((wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) &&
 (wptr[ASIZE] != wrptr3[ASIZE] ));
endmodule
endmodule

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My question is, is this code good for synthesis? Or this is merely good for behavioral modeling? Why? Can you please list all the trappings in this code that you would avoid?

Thanks.

 

[mrflibble]

Looks reasonable & synthesizable to me. Be aware though that those last three assign statements will result in combinational logic. And extra beware because those are also outputs of your module. In general it's a good idea to make the outputs of modules registered. Unless of course there's a good design reason not to do so.

 

[shaiko]

Is this code good for synthesis? Or this is merely good for behavioral modeling?

Only if "wclk" and "rclk" are the exact same clock (synchronous FIFO).
If "wclk" and "rclk" are asynchronous to each other, this design will be unreliable.

Users on this forum pointed me to this great article:
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
I suggest you read it thoroughly.

 

[ads-ee]

There's another paper on the same site that is for a FIFO2 design, I would avoid using that design as it's not a robust as the FIFO1 design. According to information I've found that FIFO2 design was sort of an exercise in using different techniques for pointer generation and comparison.