Help with the oscillation on pll charge pump output

[zhangljz]

Hello,

I am designing a PLL, but get stuck at the charge pump. I use the below structure. WHen I do transient simulation, I got oscillation on the output of charge pump. The loop filter parameters are calculated to meet to requirement of "PLL bandwidth < 1/20 reference frequency"

The detailed simulation are as below, what is the problem with this ringing?
And the charge pump has a large peak current at the falling edge of 'upb', how to solve this problem?



The switch is to setup the initial voltage


The simulation:



Thank you in advance

 

[kenambo]

hi

You are giving exact pulses for upb and i think the same for dn too. So the capacitor charges and discharges according to the pulses .

So that you are getting such output. Since normal PLL operation is self correcting these pulses are reduced gradually and in locking condition it becomes only the reset delay


And for the current peak it is caused by the sudden switching of your pulses. In general we use cascaded pairs to reduce the initial peak current of switching. It is the concept of cascade pairs.. "Shielding" It shields the loading of the switches. So you must connect your switches after the cascaded MOS fets instead of connecting to power supply and ground rails.

Thanks

 

[zhangljz]

Hi,

If we only consider pulling up the output with charge pump, the 'VCP' point will look like this, right?


On the other hand the 'VR' will also be varying, like this, right?


I am sorry to ask so basic questions, since I am new to PLL.

I think because of the resistor in loop filter, the output of charge pump is not like figures shown in tutorial books, like this


Is my design correct?

Many thanks

 

[kenambo]

yeah. you are right. Since it is not the real case , you are getting the oscillated output.

But what happens in real time is, the errors are eventually decreases. so your control voltage will become nearly constant after rising like the one you have attached in your post.

And It is good to design with cascade current mirrors to avoid current mismatch hat is very important to make your output stable.

Try some different structures too.

Thanks.