Chironex
Newbie level 3
Hello
I'm trying to EM-Analyze a microstrip-layout I've already checked in MWO earlier.
But now there is a need for a more detailed analyse.
The problems are the results: They do not quite look as they should and I am wondering if the ports and box sizes are the problem.
* I used usual ports (better take internal ones as long as box is _a lot_ bigger than layout?)
*1st try) Box size touching the layout edges
*2nd try) a lot of space between layout and box edges
*error message telling me, I need to autognd, put ports on edges ect.
-> tried "autognd" with both ports - but do I have to define reference planes afterwards if the layout is in the middle of the box, touching nothing?
(of course I have to with usual ports but with gnd reference planes??)
I hope someone can give me some hints on what I did wrong, i attached some files that hopefully show you what I could have done better : /
Kind Regards
I'm trying to EM-Analyze a microstrip-layout I've already checked in MWO earlier.
But now there is a need for a more detailed analyse.
The problems are the results: They do not quite look as they should and I am wondering if the ports and box sizes are the problem.
* I used usual ports (better take internal ones as long as box is _a lot_ bigger than layout?)
*1st try) Box size touching the layout edges
*2nd try) a lot of space between layout and box edges
*error message telling me, I need to autognd, put ports on edges ect.
-> tried "autognd" with both ports - but do I have to define reference planes afterwards if the layout is in the middle of the box, touching nothing?
(of course I have to with usual ports but with gnd reference planes??)
I hope someone can give me some hints on what I did wrong, i attached some files that hopefully show you what I could have done better : /
Kind Regards