Those "redundant bits" I imagine would be switched-in replacements for their co-named main bits. Presumably some select logic with RAM, NV or hard trim bits programmed at early test or some cal cycle if rewritable.
This paper describes the operation in detail. The redundancy reduces the C values ADC by 50% and thus chip area and boosts speed 30%.
The 3 redundant bits improve settling time & C ratio error tolerance coarse, fine and final estimation of quantization steps with 1 extra bit per nibble (4b).