[SOLVED] Help with multiplexed display

[madalin1990]

I am trying to decribe a verilog module for a multiplexed display,but i just keep doing it wrong.Here is what i have tried.If someone could tell me where is my mistake i would be grateful.

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Code Verilog - [expand]
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module selector(
clk,
rst,
an_sel,
data0,
data1,
data2,
data3,
data4,
data_out
);
 
input clk,rst;
output reg [4:0] an_sel;
output reg [2:0] data_out;
input [7:0] data0,data1,data2,data3,data4;
 
reg q;
always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)begin
    q <=3'b0;
    end  else
    if(q==3'b100)begin
    q<= 3'b0;
    end
     else begin
     q<=q+1;
     end
end
 
reg sel;
always @(q)
begin
if(q==3'b0)begin
an_sel <=5'b00001;// 5'b10000;
sel<=3'b0;
end else 
 
if(q==3'b001)begin
an_sel <= 5'b00010;//5'b01000;
sel<=3'b001;
end else
 
 if(q==3'b010)begin
an_sel <=5'b00100;// 5'b00100;
sel<=3'b010;
 
end else
if(q==3'b011)begin
an_sel <=5'b01000;//5'b00010;
sel<=3'b011;
end else 
 
begin
an_sel <=5'b10000;// 5'b00001;
sel<=3'b100;
end
 
 
end 
 
 
 
always @(sel)
begin
case(sel)
  0:data_out = data0;
  1:data_out = data1;
  2:data_out = data2;
  3:data_out = data3;
  4:data_out = data4;
  default : data_out=~8'b00111111;
  endcase
  end
endmodule

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[xtcx]

First of all, what is the problem you are facing with this logic?.

 

[mgate]

madalin1990,

I never used Verilog language, in fact I've just ended up reading basic syntax for this post...

One thing I know... It is not normal to do that many operations between different sizes variables...

for example:

reg q; is one bit variable

you are assigning to it a 3 bit value and doing logic equality operations with 3 bits values...

reg q;
always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)begin
    q <=3'b0;

You should declare it with 3bit size...


same thing appening with reg sel;

reg sel;
always @(q)
begin
if(q==3'b0)begin
an_sel <=5'b00001;// 5'b10000;
sel<=3'b0;

reg sel should also be 3bit size

finally your data_out register is 3 bit wide, and you are assigning to it a 8bit wide variable:

  0:data_out = data0;
  1:data_out = data1;
  2:data_out = data2;
  3:data_out = data3;
  4:data_out = data4;
  default : data_out=~8'b00111111;

data_out should also be 8 bit wide by this logic... makes sense 7 segments plus a dot segment

once again I never used this language.. I can only guess what You mean with the code...

anyway I suggest:

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module selector(
clk,
rst,
an_sel,
data0,
data1,
data2,
data3,
data4,
data_out
);
 
input clk,rst;
output reg [4:0] an_sel;
output reg [7:0] data_out;
input [7:0] data0,data1,data2,data3,data4;
 
reg [2:0] q;
always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)begin
    q <=3'b0;
    end  else
    if(q==3'b100)begin
    q<= 3'b0;
    end
     else begin
     q<=q+1;
     end
end
 
reg [2:0] sel;
always @(q)
begin
if(q==3'b0)begin
an_sel <=5'b00001;// 5'b10000;
sel<=3'b0;
end else 
 
if(q==3'b001)begin
an_sel <= 5'b00010;//5'b01000;
sel<=3'b001;
end else
 
 if(q==3'b010)begin
an_sel <=5'b00100;// 5'b00100;
sel<=3'b010;
 
end else
if(q==3'b011)begin
an_sel <=5'b01000;//5'b00010;
sel<=3'b011;
end else 
 
begin
an_sel <=5'b10000;// 5'b00001;
sel<=3'b100;
end
 
 
end 
 
 
 
always @(sel)
begin
case(sel)
  0:data_out = data0;
  1:data_out = data1;
  2:data_out = data2;
  3:data_out = data3;
  4:data_out = data4;
  default : data_out=~8'b00111111;
  endcase
  end
endmodule

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[madalin1990]

It worked after making those changes.
Thank you!