Help with JFET calculations

[I14R10]

Hello

I'm new here but I have some experience in electronics. I'm currently building JFET amplifier for my antenna, for 14MHz radio. And I need some help with JFET calculations. I'm using BF244A JFET https://www.fairchildsemi.com/datasheets/BF/BF244C.pdf

And I made a few calculations and it seems that if I choose V(drain) close to V(power supply), and if I choose really small current, I would get higher amplification. For example:

Idss=5mA
Id=1mA
Vd=8V
Vgs=-0.5V
gm=4*10^(-3)

and with that I get amplification factor 32


But if I take for example
Id=4mA (higher than in 1st)

Than amplification factor is only 8

So what I want to ask, does my calculations make sense? I have run it in electronics workbench and I get similar results.

 

[FvM]

does my calculations make sense?

Don't think so. You need to select a drain resistor, and you also must consider the connected load impedance. A gain of 32 would be only achieved with a drain resistor of 8k and no external load. But you need a respective higher supply voltage to get sufficient Vds. At 14 MHz, FET capacitances can't be ignored.

 

[erikl]

In first approximation, the gain (amplification factor) = gm*R_L. Even if the transconductance increases with drain current (s. Transconductance vs Drain Current on p. 3 of the dataSheet), the output resistor R_L has to decrease more, if Vsupply=const. Hence in such case the gain will decrease with increasing drain current.

 

[I14R10]

I didn't write that, but I calculated with Rd=8k ohm and Rs= 470 ohm, I think, I can't find the paper now.

Than the answer is yes, with smaller drain current, the gain is larger.

Just to clarify this - I want to use high gain by using very small drain current, since the antenna produces very little voltage. Then the second FET would be biased to half the supply voltage and half the drain current. And then the BJT transistors would take over.

Here is my latest calculation

Vgs=-0.5V
Idss=5mA
Vdd=9V
Id=2.5mA
Rs=200 ohm
Rd=3200 ohm (with Vd=8V)
gm=4*10^(-3)

amplification is 12.8

This should make sense now

 

[FvM]

With Id = 2.5 mA and Vdd = 9V, you get Vds of only 0.5 V, which is hardly suitable.

As another point, if you are designing real FET amplifiers, you should calculate it for the expectable Vgs,off and Idss range, not just assume a typical datasheet value.

 

[LvW]

Did you bypass the source resistor Rs with a capacitor? If not - you have forgotten the feedback effect in your calculation.

 

[I14R10]

With Id = 2.5 mA and Vdd = 9V, you get Vds of only 0.5 V, which is hardly suitable.

As another point, if you are designing real FET amplifiers, you should calculate it for the expectable Vgs,off and Idss range, not just assume a typical datasheet value.

Why is Vds=0.5V not good?

Did you bypass the source resistor Rs with a capacitor? If not - you have forgotten the feedback effect in your calculation.

Yes I did.

 

[FvM]

Why is Vds=0.5V not good?

Because it's in the ohmic ("triode") part of the output characteristic with low output impedance and respective low gain. Vds should be at least 2V for BF244A.

Unfortunately the characteristic isn't shown in the Fairchild datasheet. Here's the original Philips/NXP drawing:

 

[I14R10]

aah yes, now I understand. It needs to be in the saturation region