helterskelter
Newbie level 6
Hi,
I'm trying to find information on how to create a scalable V.110 rate adaption core.
Before I start with creating this from fresh I was curious to know if anybody has done anthing similar? I don't want to recreate the wheel!
Does anybody know of a company that's sell this sort of core?
Has anybody done this before and are they willing to share?
Does anybody know of any semiconductor manufactuer who makes an multi-port rate adaptor chips?
I've looked into creating one my slef and I'm fairly certain that I'll need a FIFO/RAM , state machines, baud rate generators etc. It needs to be bi-direction and switchable for the various rates. All I need now an understanding of the V.110 protocol so I can start building the necessary state machines.
Example.
(serial device) 9K6 => 64K (isdn)
(serial device) 9K6 <= 64K (isdn)
Once it can do this I'll make sure it works at all the other required rates.
Any assistance you can give would be appreciated.
Oh, I'll be using VHDL in an Altera device, most likely a cyclone FPGA.
Thanks
Helter.
I'm trying to find information on how to create a scalable V.110 rate adaption core.
Before I start with creating this from fresh I was curious to know if anybody has done anthing similar? I don't want to recreate the wheel!
Does anybody know of a company that's sell this sort of core?
Has anybody done this before and are they willing to share?
Does anybody know of any semiconductor manufactuer who makes an multi-port rate adaptor chips?
I've looked into creating one my slef and I'm fairly certain that I'll need a FIFO/RAM , state machines, baud rate generators etc. It needs to be bi-direction and switchable for the various rates. All I need now an understanding of the V.110 protocol so I can start building the necessary state machines.
Example.
(serial device) 9K6 => 64K (isdn)
(serial device) 9K6 <= 64K (isdn)
Once it can do this I'll make sure it works at all the other required rates.
Any assistance you can give would be appreciated.
Oh, I'll be using VHDL in an Altera device, most likely a cyclone FPGA.
Thanks
Helter.
