Help with a theoretical FPGA design problem!

[bsodmike]

Help with FPGA design!

Hello there!

I'm new to FPGAs but I'm wondering how one would treat this problem.

There are two buttons as input and each one has a corresponding output say SWA/SWB and LEDA/LEDB.

Basically if SWA is pushed, LEDA should be 'latched' until the system is reset. Same for SWB which would latch LEDB.

Now here's the tricky bit - if both are pushed simultaneoulsy then we 'toggle' between LEDA and LEDB for each successive simultaneous pushes.

Does one treat this like an F.S.M. problem, with Mealy model? I tried doing a state table/state diagram and hit a brick wall with the latching part.

I have come up with a design that involves simple logic but I'm wondering if there is a much better way of doing this. The way I set about it is how a caveman would - no proper planning and thinking how this would work...

So any help in solving this to give:

state diag
state table
expanded state table
minimization
final system diag

Thanks a lot!

Mike

 

[WA]

Re: Help with FPGA design!

@Mike;

What you described sounded like a J-K FF.

Look up the truth table and this will get you on your way.
Since you didn't say anything about a clock, The J-K might not help because it changes states during the clock.

Hope this helps
wa

 

[bsodmike]

Help with FPGA design!

I'll be using a D Type ff.

My current design is pretty sweet, I'll schem it up and post here after I simulate it in MAX+PLUSII sometime this week...

clock == push of button

 

[dddhacker]

Re: Help with FPGA design!

Well if you will be using the input from the switches as clock how will you set reset the flipflops. You will tie the D input to VCC or ground. It wont toggle like this.

 

[bsodmike]

Help with FPGA design!

I'll get teh schem done tomorrow. See how it works then...

Thanks,

Mike