be careful the VCO output driver capability
Frequency output change, maybe you can debug like these ways:
1. VDD pulling, please confirm the voltage supply;
2. PLL locking, if you PLL not get locked well, or loop PM not enough, the output frequency also change;
3. Load pushing: the test div-4 is build in the PLL loop, or open loop divder? please use a perfect RF proble to test
4. div-8, if it work unnorm, you can let the VDD 10% higher to test
5. your PLL loop work badly (LPF is simple 2-order) also can get large jitter
try and debug, blesh you~~