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Help! Who knows the pseudo-random binary sequence?

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FPGAs

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pseudo random binary sequence lfsr

would you please give me some datasheet or VHDL code?

thanks a lot!
 

FPGAs

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pseudorandom binary sequence xilinx

Thank you very much.

Is there any other complex pseudo-random binary sequence?
 

Buriedcode

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how to generate pseudo-random binary sequences

Hi,

echo47 hit the nail on the head.

Is there any other complex pseudo-random binary sequence?

A single LFSR of length say, 18 will generate a very long pseudo random string of 1's and 0's, but you can always 'modulate' this. Simply by using more than one LFSR.

For example, if you create two LFSR's of the same length, but with different polynomials (feedback taps), and then have a third LFSR of a shorter length who's output determines which of the other two is used in the sequence. So, our two 'big' LFSR's are A and B. The smaller one C, when it outputs a '1', the output from A is used. When C outputs a '0' the output from B is used.

Obviously, if A,B and C are all the same legth, the length of the sequence is the same as the legth of A's sequence. But...make C shorter, by 2 (so a length of 16) and the random sequence will be huge.

I'm sure there are some *.pdf's on the web for CDMA, 3G phones. They use silly pseudo-random sequences that are repeated every few days. These use multiple LFSR's.

BuriedCode.

Ps. I'm no expert, but I have build random sequence generators for testing BER of radio channels. Some of which are a few billion bits long.
 

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