Verilog Assignment Rule:
part select must constant,
but bit select no limit in procedure assign:
so can use another method,
for(ii = 0;ii<8;ii=ii+1)
if (ii == addr_i)
for(jj = 0;jj<`w;jj=jj+1)
cast[ii*`w+jj] = data_i[jj];
else
for(jj = 0;jj<`w;jj=jj+1)
cast[ii*`w+jj] = 1'bz;