From analog viewpoint an inverter can be assumed as single-ended comparator with fixed and pure defined threshold voltage, strongly depending on PVT(i.e. Vdd/2+Vos, where Vos(PVT) ~ +/-30%Vdd). To reduce this dependence an offset periodical correction method is used. That is devision a comparator desision interval into 2 parts: during first half an offset is stored on capacitor by closing analog switch between inverter input and output, during second half switch is opened and signal sign decision is produced. In SAR ADC all capacitor matrix serves for offset storing of first inverter/amplifier stage. To increase comparator accuracy an offset voltage of second inverter/amplifier stage can be done by inserting additional storage capacitor between stages and switch around second stage.