Re: Clock Design HELP!!!
In the context of a bigger circuit, the method of using multiple clocks to speed up the counter by a fixed factor is not a good one. Introducing a new clock in the design always increases the complexity and affects STA, placement and routing, scan insertion and ATPG, reset circuit design etc. It is much simpler to have two different parameter definitions so that depending on the "mode" of the counter it decrements by 1 or say by 10 on every clock edge. You would need to run the counter on the faster of the two clocks. If power saving is a concern and the difference in clock frequencies is very very large (say 1 KHz and 100MHz) then clock multiplexing might be justified.