Comment that I am trying to translate a verilog file to vhdl, but so far I am having trouble using an .h file in my vhdl code.
Someone who can help me with this problem please, leave the verilog code attached.
I haven't looked at your files, but VHDL doesn't support include files.
You should put common stuff in a package, which you then can use in any module.
.h (and verilog vh or svh files) files are usually included via use of a pre-processor that simply dumps the contents of the included file into the source file where they are included before the source is actually compiled.
VHDL has no pre-processor to do this, instead all code needs to be compiled into its own design unit (package or entity), where it becomes part of a library.
There are many tutorials out there that explain how this works.
It wouldnt be included as a libarary - a library is a collection of design units. It would be included as a package, that is compiled as a design unit into a library.
I would suggest that you write a package, translating from the .h file. Or as FvM suggested, just include it straight ion the design file.
Of course it does, because it is Verilog code, and hasnt been compiled. So it is neither a package or in a library.
You need to manually re-write it in VHDL yourself. a .h file is NOT a VHDL package - it is some text in a file on the hard disk.
Okay, if there is no other way, I will start translating my .h file to vhdl.
Another question I have is the use of "initial begin" in verilog. Is there any equivalent in vhdl for this?
Okay, if there is no other way, I will start translating my .h file to vhdl.
Another question I have is the use of "initial begin" in verilog. Is there any equivalent in vhdl for this?
IMO, if someone is using an initial block in synthesizable code then I would suspect the code to be less than quality code (i.e. it's probably garbage).
If you require that something in the RTL starts up at a particular value then use a reset and set it to that value during reset. Initial blocks should only be used in a testbench for simulation.