Help Required on Developing ethernet MAC on FPGA.

[luqman_abbas2]

Hi All!

I am intermediate to FPGA. and working on development of Ethernet Controller Using hard wire Logic on Spartan 3e 1600 Kit. I have managed Ethernet transmitter (as given on https://www.fpga4fun.com/10BASE-T0.html ) to get working. but i am stuck in development of receiver side. as the receiver circuitry is not working properly. So i couldn't proceed on the receiver any further.!

Kindly anybody can help me regarding the Ethernet receiver . Or any other Hard wire Receiver logic.


Regards.

 

[TrickyDicky]

I thought Xilinx already provided ethernet IP cores.

 

[FvM]

The thread title doesn't actually fit the linked fpga4fun project which attempts to implement MAC and PHY (except for an external differential receiver) in FPGA. By nature of the design, the concept involves some shortcomings compared to a regular 10BASE-T PHY, but I presume it can work. I think it's unavoidable to understand 10BASE-T signalling and have the necessary instruments to measure Tx and Rx signals in a design. Without specific results reported, it's impossible to give detail help.

 

[luqman_abbas2]

The thread title doesn't actually fit the linked fpga4fun project which attempts to implement MAC and PHY (except for an external differential receiver) in FPGA. By nature of the design, the concept involves some shortcomings compared to a regular 10BASE-T PHY, but I presume it can work. I think it's unavoidable to understand 10BASE-T signalling and have the necessary instruments to measure Tx and Rx signals in a design. Without specific results reported, it's impossible to give detail help.

Okay i will get back soon.

Regards!