Help regarding xilinx pace

[krishna2728]

Hi friends,

I have to connect a clk_x ,data_out[7:0],and manc_data(this is given from testbench) ,i want to know to which pins in xilinx pace i can connect all these as i am using spartan 3E
XC3s250e-4FT256


thank you in advance

 

[jimwu88]

Whihc version of ISE are you using? I would recommend using PlanAhead for pin planning.

Hi friends,

I have to connect a clk_x ,data_out[7:0],and manc_data(this is given from testbench) ,i want to know to which pins in xilinx pace i can connect all these as i am using spartan 3E
XC3s250e-4FT256


thank you in advance

 

[krishna2728]

I am using xilinx9.2 ,first i want to know how to generate the net list file in xilinx...could you please help me

 

[gongdori]

Netlist is generated after synthesizing the design. If you are using Xilinx tool, their synthesizer is called XST. You can run it in Xilinx ISE environment. If can also generate the netlist using other tools such as Precision Synthesis, Synplify, etc.

 

[krishna2728]

i have already synthesized i want the netlist file in word format

I have synthesized using xilinx-ISE simulator i dont have the XST ,

i got .ngr & .ngc formats i want to extract my netlist from these schematics is this possible .

 

[jimwu88]

Is there any particular reason you are still using ISE 9.2 (6 years ago) while the latest version is 13.4? Anyway, ISE simulator is for simulation. XST is part of ISE, so you have it and .ngr and .ngc files are genearted by XST. If you want a text version of the ngc netlist, you can run the "ngc2edif" command.

i have already synthesized i want the netlist file in word format

I have synthesized using xilinx-ISE simulator i dont have the XST ,

i got .ngr & .ngc formats i want to extract my netlist from these schematics is this possible .

 

[krishna2728]

I have attached a .edn extension file please let me know is this the netlist

 

[jimwu88]

Yes, that is an EDIF netlist.

I have attached a .edn extension file please let me know is this the netlist