help regarding this diagram

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santumevce1412

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design the circuit that produces the attached output.

whenever an i/p is detected at an edge of a clock, the o/p is to be one for that clock cycle and after that o/p is to be zero for any i/p in the remaining cycles.

pls find the diagram attached.
 

use FSM
u ll be able to do it easily
 

----------------
assign int=input|output

always @(posedge clk)
output<=int
---------------------

syntax is not accurate... but logic should be correct.

assuming that output is initialized to '0'

Added after 6 minutes:

sorry... earlier solution is wrong... the following should work... assumes all flops initialized to zero .

--------------------------
assign int_a=input|int_b;

always @(posedge clk)
begin
int_b<=int_a;
int_c<=int_b;
end

assign output=(~int_c)&int_b;
---------------------
 
the above verilog code is working thank u for u r help
i have asked one more question pls check u r inbox
 

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