illegal output or inout port connection
Hi,
sorry for the misconception, by declaring ports in testbench, i mean the same thing as how to define the datatype for the signals.
we use reg for inputs and wire for outputs in testbench. but what should we use when we have inout port in our module.
lets say i have a module name m.
module m (in,clk,out,data_bus);
input in,clk;
output out;
inout data_bus;
..........
endmodule
then to create testbench, i use
module test;
reg in,CLK;
reg [15:0] DATA_REG;
wire [15:0] DATA_BUS;
wire OUT;
m mym (in,CLK,OUT,DATA_BUS);
initial
CLK = 1'b0;
always
#5 CLK = !CLK;
initial
begin
........
DATA_BUS = 16'hfff0;
........
end
assign DATA_BUS = DATA_REG;
endmodule
this compiles OK and does not give error messeage when i load my design for simulation, but i does not give the result i want
, if i declare DATA_BUS as inout, it gives error.
hope i have now tell the problem quite clearly, tell me what to do?
thanks
sawaak