Help regarding error in ise synthesis

[kakarala]

Hi i am trying to synthesise the following code but its giving me errors.I searched for it but i couldnt find anything about this error. did anyone come across this error?

ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 52. result of operator > is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 55. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 62. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 68. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 75. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 106. result of operator = is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 107. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 114. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 121. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 128. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 135. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 144. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 153. result of operator and is not static.
ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 162. result of operator and is not static.




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.images.all;
use work.sad.all;


entity me is
port( clk : in std_logic;
rst : in std_logic;
IM_ROWS : in integer range 0 to 63 ;
IM_COLUMNS : in integer range 0 to 63;
currblk_x : in integer range 0 to 63;
currblk_y : in integer range 0 to 63;
best_sad : out integer range 0 to 4080;
mv_x : out integer range 0 to 63;
mv_y : out integer range 0 to 63);

end me;

architecture Behavioral of me is
component SAD4X4 is
port ( clk : in std_logic;
rst : in std_logic;
currblk_row : in integer range 0 to 63;
currblk_column : integer range 0 to 63;
refblk_row : in integer range 0 to 63;
refblk_column : in integer range 0 to 63;
sad : out integer range 0 to 4080);
end component;
signal a,b : integer range 0 to 63;
signal curr_sad,sad1,sad2,sad3,sad4,sad5,sad6,sad7,sad8 : integer range 0 to 4080;
signal stepsize : integer := 4;
signal p,q : integer := 256;
signal p1,q1 : integer ;
begin


-- for x in 0 to (IM_ROWS/BLK_ROWS)-1 loop
-- for y in 0 to (IM_COLUMNS/BLK_COLUMNS)-1 loop



--for x in 0 to 29 loop
-- for y in 0 to 43 loop
-- stepsize <= 4;

p <= currblk_x*(4); q <= currblk_y*(4);
a <= p; b <= q;


sad00 : SAD4X4 port map(clk => clk, rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q,sad => curr_sad);
Search :if stepsize>1 generate
sad01 : SAD4X4 port map(clk => clk, rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q,sad => curr_sad);
--curr_sad <= sumof_ad(a,b,p,q);
A :if 0 <= p-stepsize and p-stepsize<= IM_ROWS-1 generate
p1 <= p-stepsize;
sad02 : SAD4X4 port map(clk => clk, rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q,sad => sad1);
end generate;
--else
--sad1 <= 4080;
--end if;
B :if 0 <= p+stepsize and p+stepsize<= IM_ROWS-1 generate
p1 <= p+stepsize;
sad03 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q,sad => sad2);
end generate;
-- sad2 <= 4080;
-- end if;
C :if 0 <= q+stepsize and q+stepsize<= IM_COLUMNS-1 generate
q1 <= q+stepsize;
sad04 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q1,sad => sad3);
end generate;
-- else
-- sad3 <= 4080;
-- end if;
D:if 0 <= q-stepsize and q-stepsize<= IM_COLUMNS-1 generate
q1 <=q-stepsize;
sad05 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q1,sad => sad4);
end generate;
-- else
-- sad4 <= 4080;
-- end if;
process(clk)
begin
if sad1 < curr_sad then
curr_sad <= sad1;
p <= p-stepsize;
elsif sad2 < curr_sad then
curr_sad <= sad2;
p <= p+stepsize;
elsif sad3 < curr_sad then
curr_sad <= sad3;
q <= q+stepsize;
elsif sad4 < curr_sad then
curr_sad <= sad4;
q <= q-stepsize;
else
stepsize <= stepsize/2;
end if;
end process;
-- end if;
-- end process;
end generate;
-- mv rocess(clk)
-- begin
-- if( clk ='1' and clk'event ) then
search1 :if stepsize = 1 generate
x1 :if 0 <= p-stepsize and p-stepsize<= IM_ROWS-1 generate
p1 <= p-stepsize;
sad11 : SAD4X4 port map(clk => clk, rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q,sad => sad1);
end generate;
-- else
-- sad1 <= 4080;
-- end if;
x2 :if 0 <= p+stepsize and p+stepsize<= IM_ROWS-1 generate
p1 <= p+stepsize;
sad12 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q,sad => sad2);
end generate;
-- else
-- sad2 <= 4080;
-- end if;
x3 :if 0 <= q+stepsize and q+stepsize<= IM_COLUMNS-1 generate
q1 <= q+stepsize;
sad13 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q1,sad => sad3);
end generate;
-- else
-- sad3 <= 4080;
-- end if;
x4 :if 0 <= q-stepsize and q-stepsize <= IM_COLUMNS-1 generate
q1 <= q-stepsize;
sad14 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p,refblk_column => q1,sad => sad4);
end generate;
-- else
-- sad4 <= 4080;
-- end if;
x5 :if 0 <= p-stepsize and p-stepsize <= IM_ROWS-1 and 0 <= q-stepsize and q-stepsize<= IM_COLUMNS-1 generate
p1 <= p-stepsize;
q1 <= q-stepsize;
sad15 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q1,sad => sad5);
end generate;
-- sad5 <= sumof_ad(a,b,p-stepsize,q-stepsize);
-- else
-- sad5 <= 4080;
-- end if;
x6 :if 0 <= p-stepsize and p-stepsize<= IM_ROWS-1 and 0 <= q+stepsize and q+stepsize<= IM_COLUMNS-1 generate
p1 <= p-stepsize;
q1 <= q+stepsize;
sad16 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q1,sad => sad6);
end generate;
-- sad6 <= sumof_ad(a,b,p-stepsize,q+stepsize);
-- else
-- sad6 <= 4080;
-- end if;
x7 :if 0 <= p+stepsize and p+stepsize<= IM_ROWS-1 and 0 <= q-stepsize and q-stepsize <= IM_COLUMNS-1 generate
p1 <= p+stepsize;
q1 <= q-stepsize;
sad17 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q1,sad => sad7);
end generate;
-- sad7 <= sumof_ad(a,b,p+stepsize,q-stepsize);
-- else
-- sad7 <= 4080;
-- end if;
x8 :if 0 <= p+stepsize and p+stepsize<= IM_ROWS-1 and 0 <= q+stepsize and q+stepsize <= IM_COLUMNS-1 generate
p1 <= p+stepsize;
q1 <= q+stepsize;
sad18 : SAD4X4 port map(clk => clk , rst => rst,currblk_row => a,currblk_column => b,refblk_row => p1,refblk_column => q1,sad => sad8);
end generate;

-- sad8 <= sumof_ad(a,b,p+stepsize,q+stepsize);
-- else
-- sad8 <= 4080;
-- end if;
process(clk)
begin
if sad1 < curr_sad then
curr_sad <= sad1;
p <= p-stepsize;
elsif sad2 < curr_sad then
curr_sad <= sad2;
p <= p+stepsize;
elsif sad3 < curr_sad then
curr_sad <= sad3;
q <= q+stepsize;
elsif sad4 < curr_sad then
curr_sad <= sad4;
q <= q-stepsize;
elsif sad5 < curr_sad then
curr_sad <= sad5;
p <= p-stepsize;
q <= q-stepsize;
elsif sad6 < curr_sad then
curr_sad <= sad6;
p <= p-stepsize;
q <= q+stepsize;
elsif sad7 < curr_sad then
curr_sad <= sad7;
p <= p+stepsize;
q <= q-stepsize;
elsif sad8 < curr_sad then
curr_sad <= sad8;
p <= p+stepsize;
q <= q+stepsize;
end if;
end process;
end generate;


-- motion_vectors(index,0) <= p - x*(IM_ROWS/BLK_ROWS);
-- motion_vectors(index,1) <= q - y*(IM_COLUMNS/BLK_COLUMNS);
mv_x <= p - a;
mv_y <= q - b;
best_sad <= curr_sad;
-- end if;



end Behavioral;

 

[devas]

Hi,

Line 52: contains a generate statement. A generate statement must have a static (fixed) condition. You use a signal "stepsize" in this condition. A signal is not a static. Change the signal in a constant (static) and this error will be fixed.

The same applies for the other generate statements.

Devas